An embodiment relates generally to cache coherency, and more specifically, to a cache coherency protocol for allowing parallel data fetches and evictions to the same addressable index.
A cache is a component that transparently retains data elements (or simply data) so that future requests for any retained data can be served faster. A data element that is stored within a cache corresponds to a pre-defined storage location within a computer system. Such data element might be a value that has recently been computed or a duplicate copy of the same storage location that are also stored elsewhere. If requested data is contained in the cache, this is a cache hit, and this request can be served by simply reading the cache, which is comparatively faster since the cache is usually built close to its requester. Otherwise, if the data is not contained in the cache, this is a cache miss, and the data has to be fetched from a storage system medium not necessarily close to the requester, and thus is comparatively slower. In general, the greater the number of requests that can be served from the cache, the faster the overall system performance becomes.
In computing, cache coherence (also cache coherency) refers to the consistency of data stored in local caches of a shared resource. When clients in a system maintain caches of a common memory resource, issues may arise with inconsistent data. This is particularly true of central processing units (CPUs) in a multiprocessing system. If one client has a copy of a memory block from a previous read and a second client changes that memory block, the first client could be left with an invalid cache of memory without any notification of the change. Cache coherency is intended to manage such conflicts and maintain consistency between the cache and system memory.